mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-28 21:38:03 +03:00
13743b27fc
* shader_recompiler: Add more format swap modes * texture_cache: Handle stencil texture reads * emulator: Support loading font library * readme: Add thanks section * shader_recompiler: Constant buffers as integers * shader_recompiler: Typed buffers as integers * shader_recompiler: Separate thread bit scalars * We can assume guest shader never mixes them with normal sgprs. This helps avoid errors where ssa could view an sgpr write dominating a thread bit read, due to how control flow is structurized, even though its not possible in actual control flow * shader_recompiler: Implement data append/consume operations * clang format * buffer_cache: Simplify invalidation scheme * video_core: Remove some invalidation remnants * adjust
76 lines
2.5 KiB
C++
76 lines
2.5 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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void Translator::EmitExport(const GcnInst& inst) {
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if (ir.block->has_multiple_predecessors && info.stage == Stage::Fragment) {
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ir.Discard(ir.LogicalNot(ir.GetExec()));
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}
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const auto& exp = inst.control.exp;
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const IR::Attribute attrib{exp.target};
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const std::array vsrc = {
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IR::VectorReg(inst.src[0].code),
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IR::VectorReg(inst.src[1].code),
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IR::VectorReg(inst.src[2].code),
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IR::VectorReg(inst.src[3].code),
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};
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const auto swizzle = [&](u32 comp) {
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if (!IR::IsMrt(attrib)) {
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return comp;
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}
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const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
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switch (runtime_info.fs_info.mrt_swizzles[index]) {
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case MrtSwizzle::Identity:
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return comp;
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case MrtSwizzle::Alt:
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static constexpr std::array<u32, 4> AltSwizzle = {2, 1, 0, 3};
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return AltSwizzle[comp];
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case MrtSwizzle::Reverse:
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static constexpr std::array<u32, 4> RevSwizzle = {3, 2, 1, 0};
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return RevSwizzle[comp];
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case MrtSwizzle::ReverseAlt:
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static constexpr std::array<u32, 4> AltRevSwizzle = {3, 0, 1, 2};
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return AltRevSwizzle[comp];
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default:
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UNREACHABLE();
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}
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};
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const auto unpack = [&](u32 idx) {
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const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
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const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
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ir.SetAttribute(attrib, r, swizzle(idx * 2));
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ir.SetAttribute(attrib, g, swizzle(idx * 2 + 1));
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};
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// Components are float16 packed into a VGPR
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if (exp.compr) {
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// Export R, G
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if (exp.en & 1) {
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unpack(0);
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}
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// Export B, A
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if ((exp.en >> 2) & 1) {
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unpack(1);
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}
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} else {
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// Components are float32 into separate VGPRS
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u32 mask = exp.en;
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
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ir.SetAttribute(attrib, comp, swizzle(i));
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}
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}
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}
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} // namespace Shader::Gcn
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