diff --git a/rpcs3/Emu/RSX/NV47/HW/common.cpp b/rpcs3/Emu/RSX/NV47/HW/common.cpp
index a12053b5c6..45e7b001a1 100644
--- a/rpcs3/Emu/RSX/NV47/HW/common.cpp
+++ b/rpcs3/Emu/RSX/NV47/HW/common.cpp
@@ -11,6 +11,16 @@ namespace rsx
 {
 	namespace util
 	{
+		bool is_volatile_TIU(rsx::context* ctx, u32 index)
+		{
+			if (!RSX(ctx)->fs_sampler_state[index])
+			{
+				return false;
+			}
+
+			return RSX(ctx)->fs_sampler_state[index]->upload_context != rsx::texture_upload_context::shader_read;
+		}
+
 		void push_vertex_data(rsx::context* ctx, u32 attrib_index, u32 channel_select, int count, rsx::vertex_base_type vtype, u32 value)
 		{
 			if (RSX(ctx)->in_begin_end)
@@ -65,7 +75,7 @@ namespace rsx
 
 		void set_fragment_texture_dirty_bit(rsx::context* ctx, u32 arg, u32 index)
 		{
-			if (REGS(ctx)->latch == arg)
+			if (REGS(ctx)->latch == arg && !is_volatile_TIU(ctx, index))
 			{
 				return;
 			}
@@ -78,55 +88,6 @@ namespace rsx
 			}
 		}
 
-		void set_texture_configuration_command(rsx::context* ctx, u32 reg)
-		{
-			const u32 reg_index = reg - NV4097_SET_TEXTURE_OFFSET;
-			ensure(reg_index % 8 == 0 && reg_index < 8 * 16); // Only NV4097_SET_TEXTURE_OFFSET is expected
-
-			const u32 texture_index = reg_index / 8;
-
-			// FIFO args count including this one
-			const u32 fifo_args_cnt = RSX(ctx)->fifo_ctrl->get_remaining_args_count() + 1;
-
-			// The range of methods this function resposible to
-			constexpr u32 method_range = 8;
-
-			// Get limit imposed by FIFO PUT (if put is behind get it will result in a number ignored by min)
-			const u32 fifo_read_limit = static_cast<u32>(((RSX(ctx)->ctrl->put & ~3ull) - (RSX(ctx)->fifo_ctrl->get_pos())) / 4);
-
-			const u32 count = std::min<u32>({ fifo_args_cnt, fifo_read_limit, method_range });
-
-			// Clamp by the count of methods this function is responsible to
-			std::span<const u32> command_span = RSX(ctx)->fifo_ctrl->get_current_arg_ptr(count);
-			ensure(!command_span.empty() && command_span.size() <= count);
-
-			u32* const dst_regs = &REGS(ctx)->registers[reg];
-			bool set_dirty = (dst_regs[0] != REGS(ctx)->latch) ||
-				(RSX(ctx)->fs_sampler_state[texture_index] &&
-					RSX(ctx)->fs_sampler_state[texture_index]->upload_context != rsx::texture_upload_context::shader_read);
-
-			for (usz i = 1; i < command_span.size(); i++)
-			{
-				const u32 command_data = std::bit_cast<be_t<u32>>(command_span[i]);
-
-				set_dirty = set_dirty || (command_data != dst_regs[i]);
-				dst_regs[i] = command_data;
-			}
-
-			// Skip handled methods
-			RSX(ctx)->fifo_ctrl->skip_methods(static_cast<u32>(command_span.size()) - 1);
-
-			if (set_dirty)
-			{
-				RSX(ctx)->m_textures_dirty[texture_index] = true;
-
-				if (RSX(ctx)->current_fp_metadata.referenced_textures_mask & (1 << texture_index))
-				{
-					RSX(ctx)->m_graphics_state |= rsx::pipeline_state::fragment_program_state_dirty;
-				}
-			}
-		}
-
 		void set_vertex_texture_dirty_bit(rsx::context* ctx, u32 index)
 		{
 			RSX(ctx)->m_vertex_textures_dirty[index] = true;
diff --git a/rpcs3/Emu/RSX/NV47/HW/common.h b/rpcs3/Emu/RSX/NV47/HW/common.h
index e72565e488..881985c086 100644
--- a/rpcs3/Emu/RSX/NV47/HW/common.h
+++ b/rpcs3/Emu/RSX/NV47/HW/common.h
@@ -19,8 +19,6 @@ namespace rsx
 
 		void set_fragment_texture_dirty_bit(rsx::context* ctx, u32 arg, u32 index);
 
-		void set_texture_configuration_command(rsx::context* ctx, u32 reg);
-
 		void set_vertex_texture_dirty_bit(rsx::context* ctx, u32 index);
 	}
 }
diff --git a/rpcs3/Emu/RSX/NV47/HW/nv4097.h b/rpcs3/Emu/RSX/NV47/HW/nv4097.h
index 7d338a075c..db736396b9 100644
--- a/rpcs3/Emu/RSX/NV47/HW/nv4097.h
+++ b/rpcs3/Emu/RSX/NV47/HW/nv4097.h
@@ -221,16 +221,6 @@ namespace rsx
 			}
 		};
 
-		template <u32 index>
-		struct set_texture_offset
-		{
-			static void impl(context* ctx, u32 reg, u32 /*arg*/)
-			{
-				fmt::throw_exception("Unreacable!");
-				util::set_texture_configuration_command(ctx, reg);
-			}
-		};
-
 		template <u32 index>
 		struct set_fragment_texture_dirty_bit
 		{