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https://github.com/vosen/ZLUDA.git
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867e4728d5
* LLVM unit tests: add assembly files * LLVM unit tests: first attempt * LLVM unit tests: fix - parse bitcode in context * LLVM unit tests: use pretty_assertions for line-by-line diff * LLVM unit tests: Write IR to file for failed test * LLVM unit tests: just use the stack * LLVM unit tests: use MaybeUninit * LLVM unit tests: add mul24.ll * LLVM unit tests: Adjustments after review * LLVM unit tests: Include emit_llvm::Context in emit_llvm::Module * LLVM unit tests: Fix typo * LLVM unit tests: Context need not be pub
45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
declare i32 @__zluda_ptx_impl_sreg_tid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ntid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_nctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_clock() #0
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declare i32 @__zluda_ptx_impl_sreg_lanemask_lt() #0
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define amdgpu_kernel void @xor(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
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%"39" = alloca i64, align 8, addrspace(5)
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%"40" = alloca i64, align 8, addrspace(5)
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%"41" = alloca i32, align 4, addrspace(5)
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%"42" = alloca i32, align 4, addrspace(5)
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br label %1
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1: ; preds = %0
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%"43" = load i64, ptr addrspace(4) %"37", align 4
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store i64 %"43", ptr addrspace(5) %"39", align 4
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%"44" = load i64, ptr addrspace(4) %"38", align 4
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store i64 %"44", ptr addrspace(5) %"40", align 4
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%"46" = load i64, ptr addrspace(5) %"39", align 4
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%"54" = inttoptr i64 %"46" to ptr
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%"45" = load i32, ptr %"54", align 4
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store i32 %"45", ptr addrspace(5) %"41", align 4
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%"47" = load i64, ptr addrspace(5) %"39", align 4
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%"55" = inttoptr i64 %"47" to ptr
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%"30" = getelementptr inbounds i8, ptr %"55", i64 4
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%"48" = load i32, ptr %"30", align 4
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store i32 %"48", ptr addrspace(5) %"42", align 4
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%"50" = load i32, ptr addrspace(5) %"41", align 4
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%"51" = load i32, ptr addrspace(5) %"42", align 4
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%"49" = xor i32 %"50", %"51"
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store i32 %"49", ptr addrspace(5) %"41", align 4
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%"52" = load i64, ptr addrspace(5) %"40", align 4
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%"53" = load i32, ptr addrspace(5) %"41", align 4
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%"56" = inttoptr i64 %"52" to ptr
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store i32 %"53", ptr %"56", align 4
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ret void
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}
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attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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