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https://github.com/jpd002/Play-.git
synced 2025-04-28 13:47:57 +03:00
9c840f6e05
Enables larger memory size for Namco System 256 arcade machines while keeping the standard for PS2 games.
404 lines
14 KiB
C++
404 lines
14 KiB
C++
#include "Iop_SubSystem.h"
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#include "IopBios.h"
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#include "GenericMipsExecutor.h"
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#include "../psx/PsxBios.h"
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#include "../states/MemoryStateFile.h"
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#include "../Ps2Const.h"
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#include "../Log.h"
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#include "placeholder_def.h"
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using namespace Iop;
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using namespace PS2;
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#define LOG_NAME ("iop_subsystem")
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#define STATE_CPU ("iop_cpu")
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#define STATE_RAM ("iop_ram")
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#define STATE_SCRATCH ("iop_scratch")
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#define STATE_SPURAM ("iop_spuram")
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CSubSystem::CSubSystem(bool ps2Mode)
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: m_cpu(MEMORYMAP_ENDIAN_LSBF, true)
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, m_cpuArch(MIPS_REGSIZE_32)
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, m_copScu(MIPS_REGSIZE_32)
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, m_ram(new uint8[IOP_RAM_SIZE])
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, m_scratchPad(new uint8[IOP_SCRATCH_SIZE])
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, m_spuRam(new uint8[SPU_RAM_SIZE])
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, m_dmac(m_ram, m_intc)
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, m_counters(ps2Mode ? IOP_CLOCK_OVER_FREQ : IOP_CLOCK_BASE_FREQ, m_intc)
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, m_spuCore0(m_spuRam, SPU_RAM_SIZE, &m_spuSampleCache, 0)
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, m_spuCore1(m_spuRam, SPU_RAM_SIZE, &m_spuSampleCache, 1)
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, m_spu(m_spuCore0)
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, m_spu2(m_spuCore0, m_spuCore1)
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#ifdef _IOP_EMULATE_MODULES
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, m_sio2(m_intc)
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#endif
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, m_speed(m_intc)
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, m_ilink(m_intc)
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{
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if(ps2Mode)
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{
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m_bios = std::make_shared<CIopBios>(m_cpu, m_ram, m_scratchPad);
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}
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else
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{
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m_bios = std::make_shared<CPsxBios>(m_cpu, m_ram, PS2::IOP_BASE_RAM_SIZE);
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}
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m_cpu.m_executor = std::make_unique<CGenericMipsExecutor<BlockLookupOneWay>>(m_cpu, (IOP_RAM_SIZE * 4), BLOCK_CATEGORY_PS2_IOP);
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//Read memory map
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m_cpu.m_pMemoryMap->InsertReadMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x01);
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m_cpu.m_pMemoryMap->InsertReadMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x02);
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m_cpu.m_pMemoryMap->InsertReadMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x03);
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m_cpu.m_pMemoryMap->InsertReadMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x04);
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m_cpu.m_pMemoryMap->InsertReadMap(SPEED_REG_BEGIN, SPEED_REG_END, std::bind(&CSubSystem::ReadIoRegister, this, std::placeholders::_1), 0x05);
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m_cpu.m_pMemoryMap->InsertReadMap(IOP_SCRATCH_ADDR, IOP_SCRATCH_ADDR + IOP_SCRATCH_SIZE - 1, m_scratchPad, 0x06);
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m_cpu.m_pMemoryMap->InsertReadMap(HW_REG_BEGIN, HW_REG_END, std::bind(&CSubSystem::ReadIoRegister, this, std::placeholders::_1), 0x07);
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//Write memory map
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m_cpu.m_pMemoryMap->InsertWriteMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x01);
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m_cpu.m_pMemoryMap->InsertWriteMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x02);
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m_cpu.m_pMemoryMap->InsertWriteMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x03);
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m_cpu.m_pMemoryMap->InsertWriteMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x04);
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m_cpu.m_pMemoryMap->InsertWriteMap(SPEED_REG_BEGIN, SPEED_REG_END, std::bind(&CSubSystem::WriteIoRegister, this, std::placeholders::_1, std::placeholders::_2), 0x05);
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m_cpu.m_pMemoryMap->InsertWriteMap(IOP_SCRATCH_ADDR, IOP_SCRATCH_ADDR + IOP_SCRATCH_SIZE - 1, m_scratchPad, 0x06);
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m_cpu.m_pMemoryMap->InsertWriteMap(HW_REG_BEGIN, HW_REG_END, std::bind(&CSubSystem::WriteIoRegister, this, std::placeholders::_1, std::placeholders::_2), 0x07);
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//Instruction memory map
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m_cpu.m_pMemoryMap->InsertInstructionMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x01);
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m_cpu.m_pMemoryMap->InsertInstructionMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x02);
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m_cpu.m_pMemoryMap->InsertInstructionMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x03);
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m_cpu.m_pMemoryMap->InsertInstructionMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1, m_ram, 0x04);
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m_cpu.m_pArch = &m_cpuArch;
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m_cpu.m_pCOP[0] = &m_copScu;
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m_cpu.m_pAddrTranslator = &CMIPS::TranslateAddress64;
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m_dmac.SetReceiveFunction(CDmac::CHANNEL_SPU0, std::bind(&CSpuBase::ReceiveDma, &m_spuCore0, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3, PLACEHOLDER_4));
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m_dmac.SetReceiveFunction(CDmac::CHANNEL_SPU1, std::bind(&CSpuBase::ReceiveDma, &m_spuCore1, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3, PLACEHOLDER_4));
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m_dmac.SetReceiveFunction(CDmac::CHANNEL_DEV9, std::bind(&CSpeed::ReceiveDma, &m_speed, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3, PLACEHOLDER_4));
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m_dmac.SetReceiveFunction(CDmac::CHANNEL_SIO2in, std::bind(&CSio2::ReceiveDmaIn, &m_sio2, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3, PLACEHOLDER_4));
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m_dmac.SetReceiveFunction(CDmac::CHANNEL_SIO2out, std::bind(&CSio2::ReceiveDmaOut, &m_sio2, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3, PLACEHOLDER_4));
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SetupPageTable();
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}
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CSubSystem::~CSubSystem()
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{
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m_bios.reset();
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delete[] m_ram;
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delete[] m_scratchPad;
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delete[] m_spuRam;
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}
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void CSubSystem::NotifyVBlankStart()
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{
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m_bios->NotifyVBlankStart();
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m_intc.AssertLine(Iop::CIntc::LINE_VBLANK);
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}
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void CSubSystem::NotifyVBlankEnd()
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{
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m_bios->NotifyVBlankEnd();
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m_intc.AssertLine(Iop::CIntc::LINE_EVBLANK);
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}
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void CSubSystem::SaveState(Framework::CZipArchiveWriter& archive)
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{
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archive.InsertFile(new CMemoryStateFile(STATE_CPU, &m_cpu.m_State, sizeof(MIPSSTATE)));
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archive.InsertFile(new CMemoryStateFile(STATE_RAM, m_ram, IOP_RAM_SIZE));
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archive.InsertFile(new CMemoryStateFile(STATE_SCRATCH, m_scratchPad, IOP_SCRATCH_SIZE));
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archive.InsertFile(new CMemoryStateFile(STATE_SPURAM, m_spuRam, SPU_RAM_SIZE));
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m_intc.SaveState(archive);
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m_dmac.SaveState(archive);
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m_counters.SaveState(archive);
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m_spuCore0.SaveState(archive);
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m_spuCore1.SaveState(archive);
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m_ilink.SaveState(archive);
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#ifdef _IOP_EMULATE_MODULES
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m_sio2.SaveState(archive);
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#endif
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m_bios->SaveState(archive);
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}
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void CSubSystem::LoadState(Framework::CZipArchiveReader& archive)
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{
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//Read and check differences in memory to invalidate executor blocks only if necessary
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{
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auto stream = archive.BeginReadFile(STATE_RAM);
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static const uint32 bufferSize = 0x1000;
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uint8 buffer[bufferSize];
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for(uint32 i = 0; i < IOP_RAM_SIZE; i += bufferSize)
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{
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stream->Read(buffer, bufferSize);
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if(memcmp(m_ram + i, buffer, bufferSize))
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{
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m_cpu.m_executor->ClearActiveBlocksInRange(i, i + bufferSize, false);
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}
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memcpy(m_ram + i, buffer, bufferSize);
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}
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}
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archive.BeginReadFile(STATE_CPU)->Read(&m_cpu.m_State, sizeof(MIPSSTATE));
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archive.BeginReadFile(STATE_SCRATCH)->Read(m_scratchPad, IOP_SCRATCH_SIZE);
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archive.BeginReadFile(STATE_SPURAM)->Read(m_spuRam, SPU_RAM_SIZE);
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m_intc.LoadState(archive);
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m_dmac.LoadState(archive);
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m_counters.LoadState(archive);
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m_spuSampleCache.Clear();
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m_spuCore0.LoadState(archive);
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m_spuCore1.LoadState(archive);
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m_ilink.LoadState(archive);
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#ifdef _IOP_EMULATE_MODULES
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m_sio2.LoadState(archive);
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#endif
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m_bios->LoadState(archive);
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}
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void CSubSystem::Reset()
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{
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memset(m_ram, 0, IOP_RAM_SIZE);
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memset(m_scratchPad, 0, IOP_SCRATCH_SIZE);
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memset(m_spuRam, 0, SPU_RAM_SIZE);
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m_cpu.Reset();
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m_cpu.m_executor->Reset();
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m_cpu.m_analysis->Clear();
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m_spuSampleCache.Clear();
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m_spuCore0.Reset();
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m_spuCore1.Reset();
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m_spu.Reset();
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m_spu2.Reset();
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#ifdef _IOP_EMULATE_MODULES
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m_sio2.Reset();
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#endif
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m_speed.Reset();
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m_ilink.Reset();
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m_counters.Reset();
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m_dmac.Reset();
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m_intc.Reset();
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m_cpu.m_Comments.RemoveTags();
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m_cpu.m_Functions.RemoveTags();
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m_dmaUpdateTicks = 0;
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m_spuIrqUpdateTicks = 0;
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}
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void CSubSystem::SetupPageTable()
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{
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for(uint32 i = 0; i < 2; i++)
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{
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uint32 addressBit = (i == 0) ? 0 : 0x80000000;
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m_cpu.MapPages(addressBit | (PS2::IOP_RAM_SIZE * 0), PS2::IOP_RAM_SIZE, m_ram);
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m_cpu.MapPages(addressBit | (PS2::IOP_RAM_SIZE * 1), PS2::IOP_RAM_SIZE, m_ram);
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m_cpu.MapPages(addressBit | (PS2::IOP_RAM_SIZE * 2), PS2::IOP_RAM_SIZE, m_ram);
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m_cpu.MapPages(addressBit | (PS2::IOP_RAM_SIZE * 3), PS2::IOP_RAM_SIZE, m_ram);
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m_cpu.MapPages(addressBit | PS2::IOP_SCRATCH_ADDR, PS2::IOP_SCRATCH_SIZE, m_scratchPad);
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}
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}
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uint32 CSubSystem::ReadIoRegister(uint32 address)
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{
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if(address == 0x1F801814)
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{
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return 0x14802000;
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}
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else if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
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{
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return m_spu.ReadRegister(address);
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}
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else if(
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(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END) ||
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(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END) ||
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(address >= CDmac::DMAC_ZONE3_START && address <= CDmac::DMAC_ZONE3_END))
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{
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return m_dmac.ReadRegister(address);
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}
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else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
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{
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return m_intc.ReadRegister(address);
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}
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else if(
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(address >= CRootCounters::ADDR_BEGIN1 && address <= CRootCounters::ADDR_END1) ||
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(address >= CRootCounters::ADDR_BEGIN2 && address <= CRootCounters::ADDR_END2))
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{
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return m_counters.ReadRegister(address);
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}
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#ifdef _IOP_EMULATE_MODULES
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else if(address >= CSio2::ADDR_BEGIN && address <= CSio2::ADDR_END)
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{
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return m_sio2.ReadRegister(address);
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}
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#endif
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else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
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{
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return m_spu2.ReadRegister(address);
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}
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else if((address >= 0x1F801000 && address <= 0x1F801020) || (address >= 0x1F801400 && address <= 0x1F801420))
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{
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CLog::GetInstance().Print(LOG_NAME, "Reading from SSBUS.\r\n");
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}
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else if(address >= CDev9::ADDR_BEGIN && address <= CDev9::ADDR_END)
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{
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return m_dev9.ReadRegister(address);
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}
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else if(address >= SPEED_REG_BEGIN && address <= SPEED_REG_END)
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{
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return m_speed.ReadRegister(address);
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}
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else if(address >= CIlink::ADDR_BEGIN && address <= CIlink::ADDR_END)
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{
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return m_ilink.ReadRegister(address);
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}
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else
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{
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CLog::GetInstance().Print(LOG_NAME, "Reading an unknown hardware register (0x%08X).\r\n", address);
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}
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return 0;
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}
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uint32 CSubSystem::WriteIoRegister(uint32 address, uint32 value)
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{
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if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
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{
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m_spu.WriteRegister(address, static_cast<uint16>(value));
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}
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else if(
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(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END) ||
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(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END) ||
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(address >= CDmac::DMAC_ZONE3_START && address <= CDmac::DMAC_ZONE3_END))
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{
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m_dmac.WriteRegister(address, value);
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}
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else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
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{
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m_intc.WriteRegister(address, value);
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}
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else if(
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(address >= CRootCounters::ADDR_BEGIN1 && address <= CRootCounters::ADDR_END1) ||
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(address >= CRootCounters::ADDR_BEGIN2 && address <= CRootCounters::ADDR_END2))
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{
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m_counters.WriteRegister(address, value);
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}
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#ifdef _IOP_EMULATE_MODULES
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else if(address >= CSio2::ADDR_BEGIN && address <= CSio2::ADDR_END)
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{
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m_sio2.WriteRegister(address, value);
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}
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#endif
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else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
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{
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return m_spu2.WriteRegister(address, value);
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}
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else if((address >= 0x1F801000 && address <= 0x1F801020) || (address >= 0x1F801400 && address <= 0x1F801420))
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{
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CLog::GetInstance().Print(LOG_NAME, "Writing to SSBUS (0x%08X).\r\n", value);
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}
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else if(address >= CDev9::ADDR_BEGIN && address <= CDev9::ADDR_END)
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{
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m_dev9.WriteRegister(address, value);
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}
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else if(address >= SPEED_REG_BEGIN && address <= SPEED_REG_END)
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{
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m_speed.WriteRegister(address, value);
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}
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else if(address >= CIlink::ADDR_BEGIN && address <= CIlink::ADDR_END)
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{
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m_ilink.WriteRegister(address, value);
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}
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else
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{
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CLog::GetInstance().Warn(LOG_NAME, "Writing to an unknown hardware register (0x%08X, 0x%08X).\r\n", address, value);
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}
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if(
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m_intc.HasPendingInterrupt() &&
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(m_cpu.m_State.nHasException == MIPS_EXCEPTION_NONE) &&
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((m_cpu.m_State.nCOP0[CCOP_SCU::STATUS] & CMIPS::STATUS_IE) == CMIPS::STATUS_IE))
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{
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m_cpu.m_State.nHasException = MIPS_EXCEPTION_CHECKPENDINGINT;
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}
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return 0;
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}
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void CSubSystem::CheckPendingInterrupts()
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{
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if(!m_cpu.m_State.nHasException)
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{
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if(m_intc.HasPendingInterrupt())
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{
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m_bios->HandleInterrupt();
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}
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}
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}
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bool CSubSystem::IsCpuIdle()
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{
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return m_bios->IsIdle();
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}
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void CSubSystem::CountTicks(int ticks)
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{
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static const int g_dmaUpdateDelay = 10000;
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static const int g_spuIrqCheckDelay = 1000;
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m_counters.Update(ticks);
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m_speed.CountTicks(ticks);
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m_bios->CountTicks(ticks);
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m_dmaUpdateTicks += ticks;
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if(m_dmaUpdateTicks >= g_dmaUpdateDelay)
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{
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m_dmac.ResumeDma(Iop::CDmac::CHANNEL_SPU0);
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m_dmac.ResumeDma(Iop::CDmac::CHANNEL_SPU1);
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m_dmaUpdateTicks -= g_dmaUpdateDelay;
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}
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m_spuIrqUpdateTicks += ticks;
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if(m_spuIrqUpdateTicks >= g_spuIrqCheckDelay)
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{
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bool irqPending = false;
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irqPending |= m_spuCore0.GetIrqPending();
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irqPending |= m_spuCore1.GetIrqPending();
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if(irqPending)
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{
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m_intc.AssertLine(CIntc::LINE_SPU2);
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}
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else
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{
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m_intc.ClearLine(CIntc::LINE_SPU2);
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}
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m_spuIrqUpdateTicks -= g_spuIrqCheckDelay;
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}
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}
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int CSubSystem::ExecuteCpu(int quota)
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{
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int executed = 0;
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CheckPendingInterrupts();
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if(!m_cpu.m_State.nHasException)
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{
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executed = (quota - m_cpu.m_executor->Execute(quota));
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}
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if(m_cpu.m_State.nHasException)
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{
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switch(m_cpu.m_State.nHasException)
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{
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case MIPS_EXCEPTION_SYSCALL:
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m_bios->HandleException();
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assert(m_cpu.m_State.nHasException == MIPS_EXCEPTION_NONE);
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break;
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case MIPS_EXCEPTION_CHECKPENDINGINT:
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{
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m_cpu.m_State.nHasException = MIPS_EXCEPTION_NONE;
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CheckPendingInterrupts();
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//Needs to be cleared again because exception flag might be set by BIOS interrupt handler
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m_cpu.m_State.nHasException = MIPS_EXCEPTION_NONE;
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}
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break;
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}
|
|
assert(m_cpu.m_State.nHasException == MIPS_EXCEPTION_NONE);
|
|
}
|
|
return executed;
|
|
}
|