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98 lines
3.1 KiB
C++
98 lines
3.1 KiB
C++
#include "BranchTest.h"
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#include "VuAssembler.h"
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void CBranchTest::Execute(CTestVm& virtualMachine)
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{
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//Inspired by Star Ocean 3
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auto branch1HitRegister = CVuAssembler::VI8;
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auto branch2HitRegister = CVuAssembler::VI9;
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auto nextBlockAddress = 0u;
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auto branch1Address = 0u;
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auto branch2Address = 0u;
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virtualMachine.Reset();
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{
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auto microMem = reinterpret_cast<uint32*>(virtualMachine.m_microMem);
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CVuAssembler assembler(microMem);
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auto branch1Label = assembler.CreateLabel();
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auto branch2Label = assembler.CreateLabel();
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::B(branch1Label));
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::IBEQ(CVuAssembler::VI2, CVuAssembler::VI0, branch2Label));
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nextBlockAddress = assembler.GetProgramSize() * CVuAssembler::INSTRUCTION_SIZE;
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::NOP());
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assembler.Write(
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CVuAssembler::Upper::NOP() | CVuAssembler::Upper::E_BIT,
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CVuAssembler::Lower::NOP());
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::NOP());
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//Branch 1
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assembler.MarkLabel(branch1Label);
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branch1Address = assembler.GetProgramSize() * CVuAssembler::INSTRUCTION_SIZE;
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::IADDIU(branch1HitRegister, CVuAssembler::VI0, 1));
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assembler.Write(
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CVuAssembler::Upper::NOP() | CVuAssembler::Upper::E_BIT,
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CVuAssembler::Lower::NOP());
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::NOP());
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//Branch 2
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assembler.MarkLabel(branch2Label);
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branch2Address = assembler.GetProgramSize() * CVuAssembler::INSTRUCTION_SIZE;
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::IADDIU(branch2HitRegister, CVuAssembler::VI0, 1));
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assembler.Write(
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CVuAssembler::Upper::NOP() | CVuAssembler::Upper::E_BIT,
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CVuAssembler::Lower::NOP());
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assembler.Write(
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CVuAssembler::Upper::NOP(),
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CVuAssembler::Lower::NOP());
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}
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//Execute all possible blocks to make sure all possible links are here
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virtualMachine.ExecuteTest(0);
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virtualMachine.ExecuteTest(nextBlockAddress);
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virtualMachine.ExecuteTest(branch1Address);
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virtualMachine.ExecuteTest(branch2Address);
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//If VI2 is zero, should end up in branch 2 and we executed the starting instruction of branch 1
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virtualMachine.m_cpu.m_State.nCOP2VI[2] = 0;
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virtualMachine.m_cpu.m_State.nCOP2VI[branch1HitRegister] = 0;
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virtualMachine.m_cpu.m_State.nCOP2VI[branch2HitRegister] = 0;
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virtualMachine.ExecuteTest(0);
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TEST_VERIFY(virtualMachine.m_cpu.m_State.nCOP2VI[branch1HitRegister] == 1);
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TEST_VERIFY(virtualMachine.m_cpu.m_State.nCOP2VI[branch2HitRegister] == 1);
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//If VI2 not zero, should end up in branch 1
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virtualMachine.m_cpu.m_State.nCOP2VI[2] = 1;
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virtualMachine.m_cpu.m_State.nCOP2VI[branch1HitRegister] = 0;
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virtualMachine.m_cpu.m_State.nCOP2VI[branch2HitRegister] = 0;
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virtualMachine.ExecuteTest(0);
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TEST_VERIFY(virtualMachine.m_cpu.m_State.nCOP2VI[branch1HitRegister] == 1);
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TEST_VERIFY(virtualMachine.m_cpu.m_State.nCOP2VI[branch2HitRegister] == 0);
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}
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