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Implement TEQI and check traps in debug builds.

Browse source 
Better than doing absolutely nothing, though very unlikely to trigger in normal circumstances.
This commit is contained in:
Jean-Philip Desjardins 2023-02-27 15:08:49 -05:00
parent ffbd6114d9
commit 53d2d49464
5 changed files with 79 additions and 70 deletions
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21
Source/MA_MIPSIV.cpp
View file

@ -1191,8 +1191,12 @@ void CMA_MIPSIV::DSUBU()
//34
void CMA_MIPSIV::TEQ()
{
//Not implemented
assert(false);
#ifdef _DEBUG
m_codeGen->PushRel64(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
m_codeGen->PushRel64(offsetof(CMIPS, m_State.nGPR[m_nRT].nV[0]));
m_codeGen->Cmp64(Jitter::CONDITION_EQ);
CheckTrap();
#endif
}
//38
@ -1299,6 +1303,17 @@ void CMA_MIPSIV::BGEZL()
Template_BranchGez(true, true);
}
//0C
void CMA_MIPSIV::TEQI()
{
#ifdef _DEBUG
m_codeGen->PushRel64(offsetof(CMIPS, m_State.nGPR[m_nRS].nV[0]));
m_codeGen->PushCst64(static_cast<int16>(m_nImmediate));
m_codeGen->Cmp64(Jitter::CONDITION_EQ);
CheckTrap();
#endif
}
//10
void CMA_MIPSIV::BLTZAL()
{
@ -1393,7 +1408,7 @@ CMA_MIPSIV::InstructionFuncConstant CMA_MIPSIV::m_cOpRegImm[MAX_REGIMM_OPS] =
//0x00
&CMA_MIPSIV::BLTZ, &CMA_MIPSIV::BGEZ, &CMA_MIPSIV::BLTZL, &CMA_MIPSIV::BGEZL, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal,
//0x08
&CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal,
&CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::TEQI, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal,
//0x10
&CMA_MIPSIV::BLTZAL, &CMA_MIPSIV::BGEZAL, &CMA_MIPSIV::BLTZALL, &CMA_MIPSIV::BGEZALL, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal, &CMA_MIPSIV::Illegal,
//0x18

2
Source/MA_MIPSIV.h
View file

@ -33,6 +33,7 @@ protected:
static void ReflOpTarget(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
static void ReflOpRtRsImm(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
static void ReflOpRsImm(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
static void ReflOpRtImm(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
static void ReflOpRsRtOff(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
static void ReflOpRsOff(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
@ -216,6 +217,7 @@ private:
void BGEZ();
void BLTZL();
void BGEZL();
void TEQI();
void BLTZAL();
void BGEZAL();
void BLTZALL();

108
Source/MA_MIPSIV_Reflection.cpp
View file

@ -13,35 +13,34 @@ void CMA_MIPSIV::ReflOpTarget(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress,
void CMA_MIPSIV::ReflOpRtRsImm(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT;
uint16 nImm;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
sprintf(sText, "%s, %s, $%04X", CMIPS::m_sGPRName[nRT], CMIPS::m_sGPRName[nRS], nImm);
}
void CMA_MIPSIV::ReflOpRsImm(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
sprintf(sText, "%s, $%04X", CMIPS::m_sGPRName[nRS], nImm);
}
void CMA_MIPSIV::ReflOpRtImm(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRT;
uint16 nImm;
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
sprintf(sText, "%s, $%04X", CMIPS::m_sGPRName[nRT], nImm);
}
void CMA_MIPSIV::ReflOpRsRtOff(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT;
uint16 nImm;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
nAddress += 4;
sprintf(sText, "%s, %s, $%08X", CMIPS::m_sGPRName[nRS], CMIPS::m_sGPRName[nRT], (nAddress + CMIPS::GetBranch(nImm)));
@ -49,11 +48,8 @@ void CMA_MIPSIV::ReflOpRsRtOff(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress
void CMA_MIPSIV::ReflOpRsOff(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS;
uint16 nImm;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
nAddress += 4;
sprintf(sText, "%s, $%08X", CMIPS::m_sGPRName[nRS], (nAddress + CMIPS::GetBranch(nImm)));
@ -61,12 +57,9 @@ void CMA_MIPSIV::ReflOpRsOff(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress,
void CMA_MIPSIV::ReflOpRtOffRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT;
uint16 nImm;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
nAddress += 4;
sprintf(sText, "%s, $%04X(%s)", CMIPS::m_sGPRName[nRT], nImm, CMIPS::m_sGPRName[nRS]);
@ -84,12 +77,9 @@ void CMA_MIPSIV::ReflOpHintOffRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddre
void CMA_MIPSIV::ReflOpIdOffRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT;
uint16 nImm;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
nAddress += 4;
sprintf(sText, "$%02X, $%04X(%s)", nRT, nImm, CMIPS::m_sGPRName[nRS]);
@ -97,71 +87,57 @@ void CMA_MIPSIV::ReflOpIdOffRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress
void CMA_MIPSIV::ReflOpRdRsRt(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT, nRD;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nRD = (uint8)((nOpcode >> 11) & 0x001F);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint8 nRD = (uint8)((nOpcode >> 11) & 0x001F);
sprintf(sText, "%s, %s, %s", CMIPS::m_sGPRName[nRD], CMIPS::m_sGPRName[nRS], CMIPS::m_sGPRName[nRT]);
}
void CMA_MIPSIV::ReflOpRdRtSa(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nSA, nRT, nRD;
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nRD = (uint8)((nOpcode >> 11) & 0x001F);
nSA = (uint8)((nOpcode >> 6) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint8 nRD = (uint8)((nOpcode >> 11) & 0x001F);
uint8 nSA = (uint8)((nOpcode >> 6) & 0x001F);
sprintf(sText, "%s, %s, %i", CMIPS::m_sGPRName[nRD], CMIPS::m_sGPRName[nRT], nSA);
}
void CMA_MIPSIV::ReflOpRdRtRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT, nRD;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
nRD = (uint8)((nOpcode >> 11) & 0x001F);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint8 nRD = (uint8)((nOpcode >> 11) & 0x001F);
sprintf(sText, "%s, %s, %s", CMIPS::m_sGPRName[nRD], CMIPS::m_sGPRName[nRT], CMIPS::m_sGPRName[nRS]);
}
void CMA_MIPSIV::ReflOpRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
sprintf(sText, "%s", CMIPS::m_sGPRName[nRS]);
}
void CMA_MIPSIV::ReflOpRd(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRD;
nRD = (uint8)((nOpcode >> 11) & 0x001F);
uint8 nRD = (uint8)((nOpcode >> 11) & 0x001F);
sprintf(sText, "%s", CMIPS::m_sGPRName[nRD]);
}
void CMA_MIPSIV::ReflOpRdRs(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRD;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRD = (uint8)((nOpcode >> 11) & 0x001F);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRD = (uint8)((nOpcode >> 11) & 0x001F);
sprintf(sText, "%s, %s", CMIPS::m_sGPRName[nRD], CMIPS::m_sGPRName[nRS]);
}
void CMA_MIPSIV::ReflOpRsRt(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode, char* sText, unsigned int nCount)
{
uint8 nRS, nRT;
nRS = (uint8)((nOpcode >> 21) & 0x001F);
nRT = (uint8)((nOpcode >> 16) & 0x001F);
uint8 nRS = (uint8)((nOpcode >> 21) & 0x001F);
uint8 nRT = (uint8)((nOpcode >> 16) & 0x001F);
sprintf(sText, "%s, %s", CMIPS::m_sGPRName[nRS], CMIPS::m_sGPRName[nRT]);
}
@ -174,9 +150,7 @@ uint32 CMA_MIPSIV::ReflEaTarget(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddres
uint32 CMA_MIPSIV::ReflEaOffset(INSTRUCTION* pInstr, CMIPS* pCtx, uint32 nAddress, uint32 nOpcode)
{
uint16 nImm;
nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
uint16 nImm = (uint16)((nOpcode >> 0) & 0xFFFF);
nAddress += 4;
return (nAddress + CMIPS::GetBranch(nImm));
@ -403,7 +377,7 @@ INSTRUCTION CMA_MIPSIV::m_cReflRegImm[32] =
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ "TEQI", NULL, CopyMnemonic, ReflOpRsImm, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },
{ NULL, NULL, NULL, NULL, NULL, NULL },

17
Source/MIPSInstructionFactory.cpp
View file

@ -6,6 +6,12 @@
#include "BitManip.h"
#include "COP_SCU.h"
extern "C" void TrapHandler(CMIPS* context)
{
//This is just a way to inspect state when traps are happening
assert(false && "Unhandled trap.");
}
CMIPSInstructionFactory::CMIPSInstructionFactory(MIPS_REGSIZE nRegSize)
: m_regSize(nRegSize)
{
@ -63,6 +69,17 @@ void CMIPSInstructionFactory::CheckTLBExceptions(bool isWrite)
m_codeGen->EndIf();
}
void CMIPSInstructionFactory::CheckTrap()
{
m_codeGen->PushCst(0);
m_codeGen->BeginIf(Jitter::CONDITION_NE);
{
m_codeGen->PushCtx();
m_codeGen->Call(reinterpret_cast<void*>(&TrapHandler), 1, Jitter::CJitter::RETURN_VALUE_NONE);
}
m_codeGen->EndIf();
}
void CMIPSInstructionFactory::ComputeMemAccessAddr()
{
uint8 nRS = (uint8)((m_nOpcode >> 21) & 0x001F);

1
Source/MIPSInstructionFactory.h
View file

@ -33,6 +33,7 @@ protected:
void ComputeMemAccessPageRef();
void CheckTLBExceptions(bool);
void CheckTrap();
void Branch(Jitter::CONDITION);
void BranchLikely(Jitter::CONDITION);