2008-01-15 20:27:44 +00:00
|
|
|
#ifndef _PS2CONST_H_
|
|
|
|
#define _PS2CONST_H_
|
|
|
|
|
|
|
|
namespace PS2
|
|
|
|
{
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2012-09-12 01:03:53 +00:00
|
|
|
EE_RAM_SIZE = 0x02000000
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2012-09-12 01:03:53 +00:00
|
|
|
EE_CLOCK_FREQ = 0x11940000
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2021-01-02 21:35:34 +00:00
|
|
|
EE_BIOS_ADDR = 0x1FC00000,
|
2012-09-12 01:03:53 +00:00
|
|
|
EE_BIOS_SIZE = 0x00400000,
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
2008-01-15 20:27:44 +00:00
|
|
|
|
2012-05-27 04:56:16 +00:00
|
|
|
enum
|
|
|
|
{
|
2022-09-21 18:01:45 -04:00
|
|
|
//Technically, SPR isn't mapped in the EE's physical address space,
|
|
|
|
//but we map it after RAM for convenience.
|
|
|
|
EE_SPR_ADDR = EE_RAM_SIZE,
|
2012-09-12 01:03:53 +00:00
|
|
|
EE_SPR_SIZE = 0x00004000,
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
2008-11-10 01:46:02 +00:00
|
|
|
|
2020-12-04 14:56:38 -05:00
|
|
|
enum
|
|
|
|
{
|
|
|
|
GS_NTSC_HSYNC_FREQ = 15734,
|
|
|
|
GS_PAL_HSYNC_FREQ = 15625
|
|
|
|
};
|
|
|
|
|
2023-05-16 09:23:46 -04:00
|
|
|
enum
|
|
|
|
{
|
|
|
|
GPU_DOT_CLOCK_FREQ = 13305600 //Ref: NO$PSX documentation
|
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2012-09-12 01:03:53 +00:00
|
|
|
IOP_RAM_SIZE = 0x00200000
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
2008-01-15 20:27:44 +00:00
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2016-03-17 16:12:40 -07:00
|
|
|
IOP_SCRATCH_ADDR = 0x1F800000,
|
2019-01-31 13:06:16 -05:00
|
|
|
IOP_SCRATCH_SIZE = 0x00001000
|
2012-05-27 04:56:16 +00:00
|
|
|
};
|
2008-01-15 20:27:44 +00:00
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
|
|
|
{
|
|
|
|
IOP_CLOCK_BASE_FREQ = (44100 * 256 * 3),
|
2018-04-30 21:01:23 +01:00
|
|
|
IOP_CLOCK_OVER_FREQ = (48000 * 256 * 3)
|
2012-09-12 01:03:53 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2011-05-08 21:58:55 +00:00
|
|
|
VUMEM0ADDR = 0x11004000,
|
2012-05-27 04:56:16 +00:00
|
|
|
VUMEM0SIZE = 0x00001000,
|
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2015-04-04 21:18:23 -04:00
|
|
|
MICROMEM0ADDR = 0x11000000,
|
2012-05-27 04:56:16 +00:00
|
|
|
MICROMEM0SIZE = 0x00001000,
|
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2014-04-27 20:27:59 -04:00
|
|
|
VUMEM1ADDR = 0x1100C000,
|
2012-05-27 04:56:16 +00:00
|
|
|
VUMEM1SIZE = 0x00004000,
|
|
|
|
};
|
|
|
|
|
2012-09-12 01:03:53 +00:00
|
|
|
enum
|
2012-05-27 04:56:16 +00:00
|
|
|
{
|
2015-04-19 13:56:25 -07:00
|
|
|
MICROMEM1ADDR = 0x11008000,
|
2012-05-27 04:56:16 +00:00
|
|
|
MICROMEM1SIZE = 0x00004000,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum
|
|
|
|
{
|
|
|
|
SPU_RAM_SIZE = 0x00200000,
|
|
|
|
};
|
2008-01-15 20:27:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|