2015-05-06 00:54:15 -04:00
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#ifndef _VUSHARED_H_
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#define _VUSHARED_H_
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#include "../MIPSReflection.h"
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#include "../MipsJitter.h"
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#include "../uint128.h"
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#include <string.h>
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#undef ABS
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#undef MAX
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namespace VUShared
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{
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2022-07-07 16:54:22 -04:00
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//Function to emit code to handle accesses to VU1 area mapped in VU0 address space
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typedef std::function<void(CMipsJitter*, uint8, uint8)> Vu1AreaAccessEmitter;
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2017-04-11 22:28:47 -04:00
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enum OP_LATENCY
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{
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2019-08-15 12:19:46 -04:00
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LATENCY_MAC = 4,
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LATENCY_DIV = 7,
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LATENCY_SQRT = 7,
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2017-04-11 22:28:47 -04:00
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LATENCY_RSQRT = 13
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};
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2023-03-27 09:23:37 -04:00
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enum VU_UPPEROP_BIT
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{
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VU_UPPEROP_BIT_I = 0x80000000,
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2024-07-30 17:59:27 -04:00
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VU_UPPEROP_BIT_E = 0x40000000,
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VU_UPPEROP_BIT_M = 0x20000000,
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VU_UPPEROP_BIT_D = 0x10000000,
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VU_UPPEROP_BIT_T = 0x08000000,
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2023-03-27 09:23:37 -04:00
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};
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2015-05-06 00:54:15 -04:00
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enum VECTOR_COMP
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{
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VECTOR_COMPX = 0,
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VECTOR_COMPY = 1,
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VECTOR_COMPZ = 2,
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VECTOR_COMPW = 3,
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};
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2016-12-31 17:49:40 -05:00
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struct REGISTER_PIPEINFO
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2015-05-06 00:54:15 -04:00
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{
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2016-12-31 17:49:40 -05:00
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size_t value;
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size_t heldValue;
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size_t counter;
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2015-05-06 00:54:15 -04:00
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};
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2016-12-28 14:01:56 -05:00
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struct FLAG_PIPEINFO
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{
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size_t value;
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size_t index;
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size_t valueArray;
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size_t timeArray;
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};
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2015-05-06 00:54:15 -04:00
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struct OPERANDSET
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{
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2018-04-30 21:01:23 +01:00
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unsigned int writeF;
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unsigned int readF0;
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2021-02-01 17:25:11 -05:00
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unsigned int readElemF0;
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2018-04-30 21:01:23 +01:00
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unsigned int readF1;
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2020-03-02 21:18:16 -05:00
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unsigned int readElemF1;
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2018-04-30 21:01:23 +01:00
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unsigned int writeI;
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2022-09-07 09:13:03 -04:00
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unsigned int writeILsu;
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2018-04-30 21:01:23 +01:00
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unsigned int readI0;
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unsigned int readI1;
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bool syncQ;
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bool readQ;
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2018-09-02 13:11:09 -04:00
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bool syncP;
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bool readP;
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2019-10-22 08:04:52 -04:00
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bool readMACflags;
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bool writeMACflags;
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2016-08-06 00:45:32 -04:00
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//When set, means that a branch following the instruction will be
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//able to use the integer value directly
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2018-04-30 21:01:23 +01:00
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bool branchValue;
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2015-05-06 00:54:15 -04:00
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};
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struct VUINSTRUCTION;
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struct VUSUBTABLE
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{
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2018-04-30 21:01:23 +01:00
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uint32 nShift;
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uint32 nMask;
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VUINSTRUCTION* pTable;
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2015-05-06 00:54:15 -04:00
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};
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struct VUINSTRUCTION
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{
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2018-04-30 21:01:23 +01:00
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const char* name;
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VUSUBTABLE* subTable;
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void (*pGetAffectedOperands)(VUINSTRUCTION* pInstr, CMIPS* pCtx, uint32, uint32, OPERANDSET&);
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2015-05-06 00:54:15 -04:00
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};
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2019-10-22 08:04:52 -04:00
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enum COMPILEHINT
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{
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2024-12-18 11:51:32 -05:00
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COMPILEHINT_SKIP_FMAC_UPDATE = (1 << 0),
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2024-12-18 11:52:26 -05:00
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COMPILEHINT_USE_ACCURATE_ADDI = (1 << 1), //For decompression in Tri-Ace games
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2019-10-22 08:04:52 -04:00
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};
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2021-02-01 17:25:11 -05:00
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uint32 MakeDestFromComponent(uint32);
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2018-04-30 21:01:23 +01:00
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int32 GetImm11Offset(uint16);
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int32 GetBranch(uint16);
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2015-05-06 00:54:15 -04:00
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2018-04-30 21:01:23 +01:00
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void VerifyVuReflectionTable(MIPSReflection::INSTRUCTION*, VUShared::VUINSTRUCTION*, size_t);
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2015-05-06 00:54:15 -04:00
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2018-04-30 21:01:23 +01:00
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bool DestinationHasElement(uint8, unsigned int);
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void ComputeMemAccessAddr(CMipsJitter*, unsigned int, uint32, uint32, uint32);
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uint32 GetDestOffset(uint8);
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uint32* GetVectorElement(CMIPS*, unsigned int, unsigned int);
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size_t GetVectorElement(unsigned int, unsigned int);
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uint32* GetAccumulatorElement(CMIPS*, unsigned int);
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size_t GetAccumulatorElement(unsigned int);
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2015-05-06 00:54:15 -04:00
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2018-04-30 21:01:23 +01:00
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void PullVector(CMipsJitter*, uint8, size_t);
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2024-12-18 17:16:45 -05:00
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void PushBcElement(CMipsJitter*, size_t);
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2018-04-30 21:01:23 +01:00
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void PushIntegerRegister(CMipsJitter*, unsigned int);
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2023-09-07 11:06:06 -04:00
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void PullIntegerRegister(CMipsJitter*, unsigned int);
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2015-05-06 00:54:15 -04:00
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2025-03-08 17:46:19 -05:00
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void MakeComparableFromFloat(CMipsJitter*);
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2019-10-22 08:04:52 -04:00
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void TestSZFlags(CMipsJitter*, uint8, size_t, uint32, uint32);
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2015-05-06 00:54:15 -04:00
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2018-04-30 21:01:23 +01:00
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void GetStatus(CMipsJitter*, size_t, uint32);
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void SetStatus(CMipsJitter*, size_t);
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2017-01-22 21:25:10 -05:00
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2021-01-19 08:43:06 -05:00
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void ADD_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool, uint32, uint32);
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2019-10-22 08:04:52 -04:00
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void ADDA_base(CMipsJitter*, uint8, size_t, size_t, bool, uint32, uint32);
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void MADD_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool, uint32, uint32);
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void MADDA_base(CMipsJitter*, uint8, size_t, size_t, bool, uint32, uint32);
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void SUB_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool, uint32, uint32);
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void SUBA_base(CMipsJitter*, uint8, size_t, size_t, bool, uint32, uint32);
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void MSUB_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool, uint32, uint32);
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void MSUBA_base(CMipsJitter*, uint8, size_t, size_t, bool, uint32, uint32);
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void MUL_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool, uint32, uint32);
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void MULA_base(CMipsJitter*, uint8, size_t, size_t, bool, uint32, uint32);
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2015-05-06 00:54:15 -04:00
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2020-04-13 17:04:18 -04:00
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void MINI_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool);
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void MAX_base(CMipsJitter*, uint8, size_t, size_t, size_t, bool);
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2015-05-06 00:54:15 -04:00
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//Shared instructions
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2018-04-30 21:01:23 +01:00
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void ABS(CMipsJitter*, uint8, uint8, uint8);
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2019-10-22 08:04:52 -04:00
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void ADD(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void ADDbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8, uint32, uint32);
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void ADDi(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void ADDq(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void ADDA(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void ADDAbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void ADDAi(CMipsJitter*, uint8, uint8, uint32, uint32);
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2020-05-13 12:09:01 -04:00
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void ADDAq(CMipsJitter*, uint8, uint8, uint32, uint32);
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2018-04-30 21:01:23 +01:00
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void CLIP(CMipsJitter*, uint8, uint8, uint32);
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void DIV(CMipsJitter*, uint8, uint8, uint8, uint8, uint32);
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void FTOI0(CMipsJitter*, uint8, uint8, uint8);
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void FTOI4(CMipsJitter*, uint8, uint8, uint8);
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void FTOI12(CMipsJitter*, uint8, uint8, uint8);
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void FTOI15(CMipsJitter*, uint8, uint8, uint8);
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void IADD(CMipsJitter*, uint8, uint8, uint8);
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void IADDI(CMipsJitter*, uint8, uint8, uint8);
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void IAND(CMipsJitter*, uint8, uint8, uint8);
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void ILWbase(CMipsJitter*, uint8);
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void ILWR(CMipsJitter*, uint8, uint8, uint8, uint32);
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void IOR(CMipsJitter*, uint8, uint8, uint8);
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void ISUB(CMipsJitter*, uint8, uint8, uint8);
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void ITOF0(CMipsJitter*, uint8, uint8, uint8);
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void ITOF4(CMipsJitter*, uint8, uint8, uint8);
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void ITOF12(CMipsJitter*, uint8, uint8, uint8);
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void ITOF15(CMipsJitter*, uint8, uint8, uint8);
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2023-07-20 18:01:15 -04:00
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void ISWbase(CMipsJitter*, uint8, uint8);
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2018-04-30 21:01:23 +01:00
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void ISWR(CMipsJitter*, uint8, uint8, uint8, uint32);
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void LQbase(CMipsJitter*, uint8, uint8);
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void LQD(CMipsJitter*, uint8, uint8, uint8, uint32);
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2024-07-31 11:46:37 -04:00
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void LQI(CMipsJitter*, uint8, uint8, uint8, uint32, const Vu1AreaAccessEmitter& = Vu1AreaAccessEmitter());
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2019-10-22 08:04:52 -04:00
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void MADD(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MADDbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8, uint32, uint32);
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void MADDi(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MADDq(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MADDA(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MADDAbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MADDAi(CMipsJitter*, uint8, uint8, uint32, uint32);
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void MADDAq(CMipsJitter*, uint8, uint8, uint32, uint32);
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2018-04-30 21:01:23 +01:00
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void MAX(CMipsJitter*, uint8, uint8, uint8, uint8);
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void MAXbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8);
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void MAXi(CMipsJitter*, uint8, uint8, uint8);
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void MINI(CMipsJitter*, uint8, uint8, uint8, uint8);
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void MINIbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8);
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void MINIi(CMipsJitter*, uint8, uint8, uint8);
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void MOVE(CMipsJitter*, uint8, uint8, uint8);
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void MR32(CMipsJitter*, uint8, uint8, uint8);
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2019-10-22 08:04:52 -04:00
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void MSUB(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MSUBbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8, uint32, uint32);
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void MSUBi(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MSUBq(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MSUBA(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MSUBAbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MSUBAi(CMipsJitter*, uint8, uint8, uint32, uint32);
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void MSUBAq(CMipsJitter*, uint8, uint8, uint32, uint32);
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2018-04-30 21:01:23 +01:00
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void MFIR(CMipsJitter*, uint8, uint8, uint8);
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void MTIR(CMipsJitter*, uint8, uint8, uint8);
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2019-10-22 08:04:52 -04:00
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void MUL(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MULbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8, uint32, uint32);
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void MULi(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MULq(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MULA(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void MULAbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void MULAi(CMipsJitter*, uint8, uint8, uint32, uint32);
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void MULAq(CMipsJitter*, uint8, uint8, uint32, uint32);
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void OPMSUB(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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2018-04-30 21:01:23 +01:00
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void OPMULA(CMipsJitter*, uint8, uint8);
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void RINIT(CMipsJitter*, uint8, uint8);
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void RGET(CMipsJitter*, uint8, uint8);
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void RNEXT(CMipsJitter*, uint8, uint8);
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void RSQRT(CMipsJitter*, uint8, uint8, uint8, uint8, uint32);
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void RXOR(CMipsJitter*, uint8, uint8);
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void SQbase(CMipsJitter*, uint8, uint8);
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void SQD(CMipsJitter*, uint8, uint8, uint8, uint32);
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2022-07-07 16:54:22 -04:00
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void SQI(CMipsJitter*, uint8, uint8, uint8, uint32, const Vu1AreaAccessEmitter& = Vu1AreaAccessEmitter());
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2018-04-30 21:01:23 +01:00
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void SQRT(CMipsJitter*, uint8, uint8, uint32);
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2019-10-22 08:04:52 -04:00
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void SUB(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void SUBbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint8, uint32, uint32);
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void SUBi(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void SUBq(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void SUBA(CMipsJitter*, uint8, uint8, uint8, uint32, uint32);
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void SUBAbc(CMipsJitter*, uint8, uint8, uint8, uint8, uint32, uint32);
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void SUBAi(CMipsJitter*, uint8, uint8, uint32, uint32);
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2018-08-31 18:15:13 -04:00
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void WAITP(CMipsJitter*);
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2018-04-30 21:01:23 +01:00
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void WAITQ(CMipsJitter*);
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void FlushPipeline(const REGISTER_PIPEINFO&, CMipsJitter*);
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2023-05-11 10:01:48 -04:00
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void SyncPipeline(const REGISTER_PIPEINFO&, CMipsJitter*, uint32);
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2018-04-30 21:01:23 +01:00
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void CheckPipeline(const REGISTER_PIPEINFO&, CMipsJitter*, uint32);
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void QueueInPipeline(const REGISTER_PIPEINFO&, CMipsJitter*, uint32, uint32);
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void CheckFlagPipeline(const FLAG_PIPEINFO&, CMipsJitter*, uint32);
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void QueueInFlagPipeline(const FLAG_PIPEINFO&, CMipsJitter*, uint32, uint32);
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void ResetFlagPipeline(const FLAG_PIPEINFO&, CMipsJitter*);
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2015-05-06 00:54:15 -04:00
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2023-09-07 16:56:12 -04:00
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void CheckFlagPipelineImmediate(const FLAG_PIPEINFO&, CMIPS*, uint32);
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void ResetFlagPipelineImmediate(const FLAG_PIPEINFO&, CMIPS*, uint32);
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2015-05-06 00:54:15 -04:00
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//Shared addressing modes
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2018-04-30 21:01:23 +01:00
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void ReflOpFdFsI(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFdFsQ(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFdFsFt(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFdFsFtBc(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFsDstItDec(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFsDstItInc(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFtFs(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFtIs(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFtDstIsDec(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFtDstIsInc(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpClip(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpAccFsI(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpAccFsQ(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpAccFsFt(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpAccFsFtBc(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpRFsf(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpFtR(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpQFtf(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpQFsfFtf(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpIdIsIt(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpItFsf(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpItIsDst(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpItIsImm5(MIPSReflection::INSTRUCTION*, CMIPS*, uint32, uint32, char*, unsigned int);
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void ReflOpAffNone(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-06-01 20:39:18 -04:00
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void ReflOpAffWrAMfRdFsFt(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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void ReflOpAffWrAMfRdFsFtBc(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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void ReflOpAffWrAMfRdFsI(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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void ReflOpAffWrAMfRdFsQ(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-02-09 11:27:53 -05:00
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2020-03-02 20:16:11 -05:00
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void ReflOpAffWrCfRdFsFt(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-02-09 11:27:53 -05:00
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2020-03-02 20:16:11 -05:00
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void ReflOpAffWrFdRdFsFt(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-02-09 11:27:53 -05:00
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void ReflOpAffWrFdRdFsI(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-06-01 20:39:18 -04:00
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void ReflOpAffWrFdMfRdFsFt(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2023-01-05 12:19:19 -05:00
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void ReflOpAffWrFdMfRdFsFtBc(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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2021-06-01 20:39:18 -04:00
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void ReflOpAffWrFdMfRdFsI(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
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void ReflOpAffWrFdMfRdFsQ(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
|
2021-02-09 11:27:53 -05:00
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void ReflOpAffWrFtRdFs(VUINSTRUCTION*, CMIPS*, uint32, uint32, OPERANDSET&);
|
2018-04-30 21:01:23 +01:00
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VUINSTRUCTION* DereferenceInstruction(VUSUBTABLE*, uint32);
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void SubTableAffectedOperands(VUINSTRUCTION* pInstr, CMIPS* pCtx, uint32, uint32, OPERANDSET&);
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extern const char* m_sBroadcast[4];
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extern const char* m_sDestination[16];
|
2016-12-31 17:49:40 -05:00
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extern const REGISTER_PIPEINFO g_pipeInfoQ;
|
2018-08-31 17:24:03 -04:00
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extern const REGISTER_PIPEINFO g_pipeInfoP;
|
2018-04-30 21:01:23 +01:00
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|
extern const FLAG_PIPEINFO g_pipeInfoMac;
|
2020-06-01 17:47:21 -04:00
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extern const FLAG_PIPEINFO g_pipeInfoSticky;
|
2018-04-30 21:01:23 +01:00
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|
extern const FLAG_PIPEINFO g_pipeInfoClip;
|
2015-05-06 00:54:15 -04:00
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|
}
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#endif
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